# Spintronic & Beyond-CMOS Computing System Integration

**Martedì 3 e mercoledì 4 luglio****ore 14**

INRIM, Sala Conferenze

**Joseph Friedman**

NanoSpinCompute Laboratory

Department of Electrical & Computer Engineering

The University of Texas at Dallas

**Abstract**

Numerous **nanodevices** have been developed with exotic electronic and spintronic characteristics. However, it is not obvious how to best **connect these devices to each other in cascaded systems** that exploit their unique behavior.

In this three-lecture tutorial, I describe and analyze the** wide range of techniques** for cascading logic devices.

In addition to the electronic cascading mechanisms of conventional computers, this course evaluates recently proposed integration techniques for** new nanocomputing systems**. I particularly emphasize **spintronics**, in which the rich physics enable a large variety of cascading mechanisms.

In contrast to conventional presentations that follow the vertical integration of a single device from the physics to the full system performance, this course provides a cross-section of cascading techniques for numerous devices. The advantages and drawbacks of the techniques are evaluated to provide inspiration for innovative circuit designs based on novel devices.

*These lectures are intended for a general scientific/engineering audience; no background on computing or spintronics is required to understand the lectures.*

**Lecture 1Cascading Techniques in Electronic Computing**

*Computing System RequirementsHysteresisLevels of Configurability*

Diode Logic

Pull-Down Logic (DCTL/RTL/DTL/ TTL/ NMOS)

Complementary Pull-Up & Pull-Down Logic (CMOS)

Differential Logic (ECL/CML)

Transmission Logic

Dynamic Pull-Down Logic

Complementary Beyond-CMOS Logic (CNT-FET/Graphene FET/Spin-FET)

Complementary Ambipolar Logic

Threshold Logic (Differential/Memristor/Four-Gate JFET*)

Memristor Implication Logic

Complementary Resistive Switch Logic

Non-Volatile Electronics

**Lecture 2Spintronic Cascading with Magnetic Tunnel Junctions**

*Electron Spin & Magnetic DomainsBiot-Savart & Dipole CouplingSpin Currents & WavesSpin-Transfer TorqueTunneling Magnetoresistance*

Programmed MTJ Logic

Clocked MTJ Logic

Field-Programmable MTJ Logic

Spin-Torque Majority Gate Logic

“All-Spin Logic”

Domain Wall MTJ Logic

mLogic

CMAT: Complementary MTJ Logic*

**Lecture 3Alternative Spintronic Cascading Techniques**

*Non-Ferromagnetic MagnetoresistanceDomain Wall ChiralityMagnetic Skyrmions*

Magnetic Core Logic

Complementary Spin-FET Logic

Spin Wave Logic

Nanomagnet Logic (MQCA)

Magnetic Domain Wall Logic

Domain Wall Chirality Logic

Shape-Based Magnetic Skyrmion Logic

Domain Wall Magnetic Skyrmion Logic

Magnetic Skyrmion Majority Gate Logic

Spin Accumulation Logic

Bilayer Avalanche Diode Logic

Spin-Diode Logic*(All-Carbon Spin Logic*)

Emitter-Coupled Spin-Transistor Logic*

*Logic families proposed by the speaker; *background material in italics*

**Biographical Sketch**

Dr. Joseph S. Friedman is an assistant professor of Electrical & Computer Engineering at The University of Texas at Dallas.

He holds a Ph.D. and M.S. in Electrical & Computer Engineering from Northwestern University and undergraduate degrees from Dartmouth College.

He was previously a CNRS Research Associate with Université Paris-Saclay, a guest scientist at RWTH Aachen University, and worked on logic design automation at Intel Corporation.

He is a member of the editorial board of the Microelectronics Journal, the technical program committees of SPIE Spintronics, DAC, NANOARCH, GLSVLSI, and ICECS, and the ISCAS review committee.

He has also been awarded a Fulbright Postdoctoral Fellowship.